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EtronTech Features * Single power supply voltage of 2.7V to 3.6V * Power down features using CE1# and CE2 * Low operating current : 30mA(max for 55 ns) * Maximum Standby current : 10A at 3.6 V * Data retention supply voltage: 1.5V to 3.6V * Direct TTL compatibility for all input and output * Wide operating temperature range: -40C to 85C * Package type: 48-ball TFBGA, 6x8mm EM562161 128K x 16 Low Power SRAM Preliminary, Rev 1.0 07/2001 circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE1#) is asserted high or (CE2) is asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from -40C to 85C, the EM562161 can be used in environments exhibiting extreme temperature conditions. Ordering Information Part Number EM562161BC-55 EM562161BC-70 Speed 55 ns 70 ns IDDS2 10 A 10 A Package 6x8 BGA 6x8 BGA Pin Configuration 48-Ball BGA (CSP), Top View 1 2 3 4 5 6 Pin Description Symbol A0 - A16 DQ0 - DQ15 CE1#, CE2 OE# WE# LB#, UB# GND VDD NC Function Address Inputs Data Inputs / Outputs Chip Enable Inputs Output Enable Read / Write Control Input Data Byte Control Inputs Ground Power Supply No Connection A LB # O E# A0 A1 A2 CE 2 B DQ 8 UB # A3 A4 CE1 # DQ 0 C DQ 9 DQ 1 0 A5 A6 DQ 1 DQ 2 D GN D DQ 1 1 NC A7 DQ 3 VD D E V DD DQ 1 2 NC A 16 DQ 4 G ND F DQ 1 4 DQ 1 3 A 14 A 15 DQ 5 DQ 6 Overview The EM562161 is a 2,097,152-bit SRAM organized as 131,072 words by 16 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.7V to 3.6V power supply. Advanced G DQ 1 5 NC A 12 A 13 WE# DQ 7 H NC A8 A9 A 10 A1 1 NC Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Block Diagram EM562161 A0 VDD MEMORY CELL ARRAY 2,048X64X16 (2,097,152) A16 GND DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 SENSE AMP DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 CO LUMN ADDRESS DECO DER WE# UB# LB# OE# CE1# CE2 POWER DO WN CIRCU IT Preliminary 2 Rev 1.0 July 2001 EtronTech Operating Mode Mode CE1# CE2 OE# WE# LB# L Read L H L H H L L Write L H X L H L Output Deselect L H Standby X L H X L H H X X X H X X X X X X H UB# L L H L L H X X X H High-Z High-Z DQ0~DQ7 DOUT High-Z DOUT DIN High-Z DIN High-Z DOUT DOUT High-Z DIN DIN High-Z High-Z EM562161 DQ8~DQ15 Power Active Active Active Active Active Active Active Standby Note: X = don't care. H=logic high. L=logic low. Absolute Maximum Ratings Supply voltage, VDD Input voltages, VIN Input and output voltages, VI/O Operating temperature, TOPR Storage temperature, TSTRG Soldering Temperature (10s), TSOLDER Power dissipation, PD -0.3 to +4.6V -0.3 to +4.6V -0.5 to VDD +0.5V -40 to +85C -55 to +150C 240C 0.6 W DC Recommended Operating Conditions (Ta=-40 C to 85 C) Symbol VDD VIH VIL VDR Parameter Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage Min 2.7 2.2 -0.3 (2) Typ - - - - Max 3.6 VDD + 0.3 0.6 3.6 (1) Unit V V V V 1.5 Note: (1) Overshoot : VDD +2.0V in case of pulse width 20ns (2) Undershoot : -2.0V in case of pulse width 20ns Preliminary 3 Rev 1.0 July 2001 EtronTech DC Characteristics (Ta = -40 C to 85 C, VDD = 2.7V to 3.6V) Parameter Input low current Output low voltage Output high voltage Symbol IIL VOL VOH IIN = 0V to VDD IOL = 2.1 mA IOH = -1.0 mA VDD = 3.6 V , IDD1 Operating current IDD2 IDDS1 Standby current Notes: * Typical value are measured at Ta = 25C, and not 100% tested. ** In standby mode with CE1# VDD - 0.2V, these limits are assured for the condition CE2 VDD - 0.2V or CE2 0.2V. IDDS2** (Note) CE1# = VIL and CE2 = VIH and IOUT = 0mA Other Input = VIH / VIL CE1# = VIH or CE2 = VIL CE1# VDD - 0.2V or CE2 0.2V, or LB# = UB# VDD - 0.2V 55 ns 70 ns Test Conditions Min -1 2.2 - - - - - EM562161 Typ* - - - 15 10 - - 1 Max Unit 1 0.4 - 30 25 4 0.5 10 mA A mA A V V Cycle time = min Cycle time = 1s Capacitance (Ta = 25 C; f = 1 MHz) Parameter Input capacitance Output capacitance Symbol CIN Min - Typ - Max 10 Unit pF Test Conditions VIN = GND COUT - - 10 pF VOUT = GND Notes: This parameter is periodically sampled and is not 100% tested. Preliminary 4 Rev 1.0 July 2001 EtronTech Read Cycle Symbol tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH Write Cycle Symbol tWC tWP tCW tBW tAS tWR tWHZ tOW tDS tDH Write cycle time Write pulse width Chip Enable to end of write Data Byte Control to end of Write Address setup time Write Recovery time WE# Low to Output in High-Z WE# High to Output in Low-Z Data Setup Time Data Hold Time Parameter 55 40 45 45 0 0 - 5 25 0 Read cycle time Address access time Chip Enable (CE1#) Access Time Chip Enable (CE2) Access Time Output enable access time Data Byte Control Access Time Chip Enable Low to Output in Low-Z Output enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Parameter 55 - - - - - 10 3 5 - - - 10 EM562161 AC Characteristics and Operating Conditions (Ta = -40 C to 85 C, V DD = 2.7V to 3.6V) EM562161 -55 -70 Min Max Min Max - 55 55 55 25 55 - - - 20 20 20 - 70 - - - - - 10 3 5 - - - 10 - 70 70 70 35 70 - - - 25 25 25 - ns Unit EM562161 -55 -70 Min Max Min Max - - - - - - 25 - - - 70 55 60 60 0 0 - 5 30 0 - - - - - - 30 - - - Unit ns AC Test Condition * Output load : 50pF + one TTL gate * Input pulse level : 0.4V, 2.4V * Timing measurements : 0.5 x VDD * tR, tF : 5ns Preliminary 5 Rev 1.0 July 2001 EtronTech Read Cycle (See Note 1) t RC EM562161 A ddr es s tA A tO H t CO 1 C E 1# CE 2 t CO 2 t HZ t OE O E# t OH Z t BA U B # , LB # t B LZ t O LZ t LZ t BHZ D O UT V AL ID DA TA OUT Preliminary 6 Rev 1.0 July 2001 EtronTech Write Cycle1 (WE# Controlled)(See Note 4) tWC EM562161 A d d r es s t AS tW P tW R W E# tC W C E1# C E2 tC W tB W U B# , LB# tW H Z tO W D O UT ( Se e No te 2 ) (S e e N ot e 3) t DS tD H D IN ( Se e Not e 5 ) V A LI D D A TA I N (S e e N ot e 5 ) Preliminary 7 Rev 1.0 July 2001 EtronTech Write Cycle 2 (CE1# Controlled)(See Note 4) tW C EM562161 A d d r e ss tA S tWP tWR W E# t CW C E1# C E2 t CW tB W U B# , LB# t B LZ t W HZ D O UT tL Z t DS t DH D IN (S e e No te 5) V AL I D DA T A IN Preliminary 8 Rev 1.0 July 2001 EtronTech Write Cycle 3 (CE2 Controlled)(See Note 4) tW C EM562161 A d d r e ss tA S tWP tWR W E# t CW C E1# C E2 t CW t W HZ D O UT tL Z t DS t DH D IN (S e e No te 5) V AL I D DA T A IN Preliminary 9 Rev 1.0 July 2001 EtronTech Write Cycle4 (UB#, LB# Controlled)(See Note 4) tW C EM562161 A d d r e ss tA S tWP tWR W E# t CW C E1# C E2 t CW tB W U B# , LB# t B LZ t W HZ D O UT tL Z t DS t DH D IN (S e e No te 5) V AL I D DA T A IN Note: 1. WE# remains HIGH for the read cycle. 2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. 3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. 4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 10 Rev 1.0 July 2001 EtronTech Data Retention Characteristics (Ta = -40 C to 85 C) Symbol Data Retention Supply Voltage Parameter CE1# VDD - 0.2V, CE2 0.2V, VIN VDD - 0.2V or VIN 0.2V VDD = 1.5V, CE1# VDD - 0.2V, CE2 0.2V, VIN VDD - 0.2V or VIN 0.2V Min EM562161 Typ Max Unit VDR 1.5 - 3.6 V IDR tSDR tRDR Data Retention Current - 0 tRC 0.5 - - 3.0 - - A ns ns Chip Deselect to Data Retention Mode Time Recovery Time CE1# Controlled Data Retention Mode tS D R V DD 2. 7V D a ta R e t e n t io n M o d e tR D R 2. 2V V DR C E1 # G ND N o te 1 CE2 Controlled Data Retention Mode V DD 2.7V t CE 2 S DR t RDR Dat a Ret ent ion M ode V DR N o te 2 0 .4 V G ND Note: 1. CE1# VDD - 0.2V or UB# = LB# VDD - 0.2V 2. CE2 0.2V Preliminary 11 Rev 1.0 July 2001 EtronTech Package Diagrams 48-Ball (6mm x 8mm) BGA Units in mm TOP VIEW EM562161 BOTTOM VIEW 0.10 S 0.25 S C C PIN 1 C O R N E R A B PIN 1 C O R N E R 0.30 3 4 5 6 6 5 4 3 0.05(48X) 2 1 1 2 -B0.75 3.75 - A0.20(4X) 0.10 -CSEATING PL ANE Preliminary 12 Rev 1.0 July 2001 |
Price & Availability of EM562161 |
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